X: A Comprehensive Analytic Model for Parallel Machines

Research output: Contribution to book/conference proceedings/anthology/reportConference contributionContributedpeer-review

Contributors

  • Ang Li - , Eindhoven University of Technology (Author)
  • Shuaiwen Leon Song - , Pacific Northwest National Laboratory (Author)
  • Eric Brugel - , Rutgers - The State University of New Jersey, New Brunswick (Author)
  • Akash Kumar - , Chair of Processor Design (cfaed) (Author)
  • Daniel Chavarria-Miranda - , Pacific Northwest National Laboratory (Author)
  • Henk Corporaal - , Eindhoven University of Technology (Author)

Abstract

To continuously comply with Moore's Law, modern parallel machines become increasingly complex. Effectively tuning application performance for these machines therefore becomes a daunting task. Moreover, identifying performance bottlenecks at application and architecture level, as well as evaluating various optimization strategies, are becoming extremely difficult when the entanglement of numerous correlated factors is being presented. To tackle these challenges, we present a visual analytical model named "X". It is intuitive and sufficiently flexible to track all the typical features of a parallel machine. Different from the conventional analytic models that focus on the temporal state of a representative core or thread, our proposed X-model concentrates on the spatial state of the parallel machines - the distribution of concurrent threads among different subsystems of these machines, while predicting the overall throughput based on such state. One major highlight of our model is its tractability as it only requires a small number of essential parameters from the application and architecture. Meanwhile, it is able to effectively help users investigate the combined-effects of different types of parallelism: the instruction-level-parallelism (ILP), the thread-level-parallelism (TLP), the memory-level-parallelism (MLP) and the data-level-parallelism (DLP). Through the X-model, developers and architects can quickly draw an intuitive figure called X-graph to identify performance bottlenecks and play "what-if " scenarios to evaluate the effectiveness of the proposed optimization techniques by investigating their individual and combined effects.

Details

Original languageEnglish
Title of host publicationProceedings - 2016 IEEE 30th International Parallel and Distributed Processing Symposium, IPDPS 2016
PublisherIEEE, New York [u. a.]
Pages242-252
Number of pages11
ISBN (electronic)9781509021406
Publication statusPublished - 18 Jul 2016
Peer-reviewedYes

Publication series

Series2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS)

Conference

Title30th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2016
Duration23 - 27 May 2016
CityChicago
CountryUnited States of America

Keywords

Research priority areas of TU Dresden

ASJC Scopus subject areas