Vertical IP Protection of the Next-Generation Devices: Quo Vadis?
Research output: Contribution to book/Conference proceedings/Anthology/Report › Conference contribution › Contributed › peer-review
Contributors
Abstract
With the advent of 5G and IoT applications, there is a greater thrust in terms of hardware security due to imminent risks caused by high amount of intercommunication between various subsystems. Security gaps in integrated circuits, thus represent high risks for both-the manufacturers and the users of electronic systems. Particularly in the domain of Intellectual Property (IP) protection, there is an urgent need to devise security measures at all levels of abstraction so that we can be one step ahead of any kind of adversarial attacks. This work presents IP protection measures from multiple perspectives-from system-level down to device-level security measures, from discussing various attack methods such as reverse engineering and hardware Trojan insertions to proposing new-age protection measures such as multi-valued logic locking and secure information flow tracking. This special session will give a holistic overview at the current state-of-the-art measures and how well we are prepared for the next generation circuits and systems.
Details
Original language | English |
---|---|
Title of host publication | Proceedings of the 2021 Design, Automation and Test in Europe, DATE 2021 |
Pages | 1905-1914 |
Number of pages | 10 |
ISBN (electronic) | 9783981926354 |
Publication status | Published - 1 Feb 2021 |
Peer-reviewed | Yes |
External IDs
Scopus | 85111038055 |
---|