Variability analysis — Prediction method for nanoscale triple gate FinFETs

Research output: Contribution to book/Conference proceedings/Anthology/ReportConference contributionContributedpeer-review

Contributors

  • D. Tassis - , Aristotle University of Thessaloniki (Author)
  • I. Messaris - , Chair of Fundamentals of Electronics, Aristotle University of Thessaloniki (Author)
  • N. Fasarakis - , Aristotle University of Thessaloniki (Author)
  • S. Nikolaidis - , Aristotle University of Thessaloniki (Author)
  • G. Ghibaudo - , Centre for Radiofrequencies, Optic and Micro-nanoelectronics in the Alps (IMEP-LaHC) (Author)
  • C. Dimitriadis - , Aristotle University of Thessaloniki (Author)

Abstract

We expanded our analytical compact model for the drain current of undoped or lightly doped nanoscale FinFETs, in order to predict and decompose variability in the electrical characteristics of FinFETs. The model has been evaluated by comparison to TCAD simulated devices with predefined variability. Successful application to experimental data of FinFETs with fin width Wfin= 15 nm, gate length LG =30 nm, equivalent gate oxide thickness tox = 1.7 nm and fin height Hfin= 65 nm, has attributed their behavior to geometrical variations (of LG, Wfin) and variability in the metal gate work function (Φm). Furthermore, variability of FinFETs having different number of fins (2-50) and fin's pitch (200-1000 nm) has been investigated.

Details

Original languageEnglish
Title of host publication2014 29th International Conference on Microelectronics Proceedings - MIEL 2014
PublisherWiley-IEEE Press
Pages99-102
Number of pages4
ISBN (print)978-1-4799-5293-9
Publication statusPublished - 14 May 2014
Peer-reviewedYes

Conference

Title2014 29th International Conference on Microelectronics Proceedings - MIEL 2014
Duration12 - 14 May 2014
LocationBelgrade, Serbia

External IDs

Scopus 84904660056

Keywords

Keywords

  • FinFETs, Logic gates, Standards, Threshold voltage, Input variables, Analytical models, Metals