Very early in the hardware development lifecycle, highly abstract simulations are essential to evaluate the performance and functionality of complex designs before they are implemented physically. For Multi-Processor System-on-Chip (MPSoC) designs that incorporate Network-on-Chip (NoC) architectures and RISC-V processors, such simulation platforms are needed. In this work, we extend and combine the PANACA simulation platform with a RISC-V Virtual Prototype to create a highly efficient and flexible MPSoC simulation platform written in SystemC-TLM. This simulation platform is capable of running a variety of applications, e.g. machine learning application, and can even support the use of real-time operating systems such as FreeRTOS. The developed memory mapped network adapters with and without interrupt support provide a seamless interface between the RISC-V processors and the NoC and enables efficient communication between the components via a unified API. This API is written in such a way that the application that uses it can be applied to simulation and hardware without the need to change the application code. Our novel simulation platform has undergone extensively testing against diverse use cases, hardware implementation, and experimental simulations, establishing its accuracy and reliability as an invaluable tool for early-stage hardware development and research.