This paper presents the analysis, design, and characterization of an on-chip ultra-low-power clock oscillator for sensor nodes, implemented in 130 nm BiCMOS technology. The design employs a multi-stacked inverter-based ring oscillator topology which utilizes variable RC features to tune the oscillation frequency. It is demonstrated that incorporating resistive coupling in the inverter stages helps to minimize frequency deviation around 12.1-13.5% for 10% of power supply variations and consequently achieves frequency stability improvement. To the best knowledge of the authors, this is the first time that a multi-stacked technique is utilized in the inverter stages of an oscillator to make the leakage current negligible reducing power consumption. With an adaptive delay line, the design is enabled to produce an adjustable duty-cycling output. The proposed oscillator consumes 510pW from a 0.35V power supply at 810 Hz operation frequency and achieves a power efficiency of 0.63 nW/kHz, positioning it among the most efficient Hz-to-kHz oscillators. The design occupies an area of 0.038 mm2.