Ultra Low Power < 9 nW Adaptive Duty Cycling Oscillator in 22 nm FDSOI CMOS Technology using Back Gate Biasing
Research output: Contribution to book/Conference proceedings/Anthology/Report › Conference contribution › Contributed › peer-review
Contributors
Abstract
An ultra low power ring oscillator with less than 9nW of DC power at a supply of 0.5 V for generating duty cycle signals for wake-up receivers is presented. It uses the possibility of FDSOI technologies to bias the transistor back gate separately to change the frequency in a wide range from 7..62 kHz and pulse time within 90..240 ns. The circuit has a good compensation of drain current over temperature, which stabilizes the frequency and pulse time. The circuit is fabricated in a 22 nm FDSOI technology. The core area occupies only 40 μm × 80 μm.
Details
| Original language | English |
|---|---|
| Title of host publication | 2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021 |
| Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| ISBN (electronic) | 978-1-7281-7670-3 |
| ISBN (print) | 978-1-7281-7671-0 |
| Publication status | Published - 21 Feb 2021 |
| Peer-reviewed | Yes |
Conference
| Title | 12th IEEE Latin American Symposium on Circuits and Systems |
|---|---|
| Abbreviated title | LASCAS 2021 |
| Conference number | 12 |
| Duration | 22 - 25 February 2021 |
| Location | Online |
| City | Arequipa |
| Country | Peru |
Keywords
ASJC Scopus subject areas
Keywords
- 22 nm FDSOI, Clock generator, CMOS integrated circuits, low power, low voltage, low-power wireless, sensor networks, wake-up radios, wake-up receivers