Transactional memory is regarded as a very promising technology to deal with concurrency control in future multicore and manycore systems. While a lot of software, hardware, and hybrid transactional memory implementations have been proposed and analyzed, the silver bullet still hasn't been found. The main reason is that the performance of transactional memory significantly depends on the actual application scenario. TMPL is a product line of transactional memory implementations for configurable hardware platforms, mainly aimed at the domain of embedded systems. It facilitates the derivation of various kinds of transactional memory with a large variety of strategies for conflict detection, conflict resolution, and versioning, from a common platform. Thereby, developers can experiment with different strategies and select one that is most efficient for a given workload profile. This paper presents the underlying product line development process, TMPL's structure, and an early quantitative evaluation of our FPGA-based implementation.