Timing Synchronization and Detection for Systems with 1-bit Quantization and Runlength Coding

Research output: Contribution to book/Conference proceedings/Anthology/ReportConference contributionContributedpeer-review

Abstract

Future communications systems are expected to utilize very large bandwidths, increasing the power consumption of analog-to-digital converters (ADCs). To address this, receivers employing temporally oversampled 1-bit quantization promise reduced power consumption due to simplified ADC circuitry. However, 1-bit ADCs introduce a non-linearity to the system, necessitating the redevelopment of most receiver algorithms. This paper extends prior work on timing synchronization for receivers with 1-bit ADCs, evaluating the mutual information rate over an equivalent modulation channel using two synchronization and detection approaches: i) interpolation and decimation based synchronization followed by soft-output detection, and ii) Bahl Cocke Jelinev Raviv (BCJR) algorithm-based joint synchronization and detection. Both approaches perform well, with the former being more computationally efficient. Additionally, we study the mutual information rate between the transmitter and the 1-bit ADC output, serving as an upper limit on the synchronizer performance.

Details

Original languageEnglish
Title of host publication2024 IEEE 25th International Workshop on Signal Processing Advances in Wireless Communications, SPAWC 2024
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages421-425
Number of pages5
ISBN (electronic)9798350393187
Publication statusPublished - 2024
Peer-reviewedYes

Publication series

SeriesIEEE Workshop on Signal Processing Advances in Wireless Communications (SPAWC)
ISSN1948-3244

Workshop

Title25th IEEE International Workshop on Signal Processing Advances in Wireless Communications
Abbreviated titleSPAWC 2024
Conference number25
Duration10 - 13 September 2024
Website
LocationReal Collegio
CityLucca
CountryItaly