With rising trends of moving AI inference to the edge, due to communication and privacy challenges, there has been a growing focus on designing low-cost Edge-AI. Given the diversity of application areas at the edge, FPGA-based systems are increasingly used for high-performance inference. Similarly, approximate computing has emerged as a viable approach to achieve disproportionate resource gains by utilizing the applications' inherent robustness. However, most related research has focused on selecting the appropriate approximate operators for an application from a set of ASIC-based designs. This approach fails to leverage the FPGA's architectural benefits and limits the scope of approximation to already existing generic designs. To this end, we propose an AI-based approach to synthesizing novel approximate operators for FPGA's Look-up-table-based structure. Specifically, we use state-of-the-art generative networks to search for constraint-aware arithmetic operator designs optimized for FPGA-based implementation. With the proposed GANs, we report up to 49% faster training, with negligible accuracy degradation, than related generative networks. Similarly, we report improved hypervolume and increased pareto-front design points compared to state-of-the-art approaches to synthesizing approximate multipliers.
|Title of host publication||ASPDAC '23: Proceedings of the 28th Asia and South Pacific Design Automation Conference|
|Number of pages||8|
|Publication status||Published - 16 Jan 2023|
|Series||Asia and South Pacific Design Automation Conference (ASP-DAC)|
Research priority areas of TU Dresden
ASJC Scopus subject areas
- AI-based Exploration, Approximate Computing, Arithmetic Operator Design, Circuit Synthesis