This work presents a real-time 100Base-TX Ethernet physical layer (PHY) transceiver chip implemented in a 180-nm technology. The PHY chip implements highly accurate hardware timestamping by using an 8-bit digital-to-phase converter (DPC) generating 256 phases of the 125 MHz system clock. Using these clock phases, spaced 31.25 ps apart from each other, phase relationships can be evaluated to timestamp ingress and egress frames with improved resolution. Connected by up to 120-m-long category five unshielded twisted-pair cables, two of these PHY chips are used to demonstrate the synchronization in a two-node scenario. A proportional-integral (PI)-clock servo is used at the slave for the synchronization. To optimize the performance, the parameters of the controller need to be chosen carefully. To do so, a simple model is used to find a suitable bandwidth of the controller as a tradeoff between the noise of the timestamping and the noise of the oscillator. All in all, a synchronization accuracy with a standard deviation of only 64 ps and a mean offset of well below 100 ps is achieved in the given scenario. To the best of our knowledge, this is the highest synchronization accuracy over copper-based Ethernet reported to date.