Split-cost communication model for improved MPSoC application mapping
Research output: Contribution to book/conference proceedings/anthology/report › Conference contribution › Contributed › peer-review
Contributors
Abstract
Automated mapping of dataflow applications to state-of-the-art, heterogeneous Multiprocessor Systems on Chip (MPSoCs) with complex interconnects and communication means is an ongoing research endeavor. We implement, measure and analyze three different communication libraries for a representative, off-the-shelf platform of this kind. The results of the analysis are used to show the need of a new cost model to properly characterize inter-task communication. Afterwards, this paper presents an algorithm to solve the mapping problem jointly for computation and communication using this cost model. A case study with four real streaming applications shows that the obtained mapping is able to reduce the execution time. Compared to a mapping decision where all channels are mapped to shared memory, the makespan fell down up to 10 % due to an automated selection of a more appropriate communication library.
Details
Original language | English |
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Title of host publication | 2013 International Symposium on System-on-Chip, SoC 2013 - Proceedings |
Publisher | IEEE Computer Society, Washington |
ISBN (print) | 9781479911899 |
Publication status | Published - 2013 |
Peer-reviewed | Yes |
Externally published | Yes |
Conference
Title | 2013 15th International Symposium on System-on-Chip, SoC 2013 |
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Duration | 23 - 24 October 2013 |
City | Tampere |
Country | Finland |
External IDs
ORCID | /0000-0002-5007-445X/work/141545589 |
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