Speculation for Parallelizing Runtime Checks
Research output: Contribution to conferences › Paper › Contributed › peer-review
Contributors
Abstract
We present and evaluate a framework, ParExC, to reduce
the runtime penalties of compiler generated runtime checks. An obvious
approach is to use idle cores of modern multi-core CPUs to parallelize
the runtime checks. This could be accomplished by (a) parallelizing the
application and in this way, implicitly parallelizing the checks, or (b) by
parallelizing the checks only. Parallelizing an application is rarely easy
and frameworks that simplify the parallelization, e.g., like software trans-
actional memory (STM), can introduce considerable overhead. ParExC is
based on alternative (b). We compare it with an approach using a trans-
actional memory-based alternative. Our experience shows that ParExC
is not only more efficient than the STM-based solution but the manual
effort for an application developer to integrate ParExC is lower. ParExC
has – in contrast to similar frameworks – two noteworthy features that
permit a more efficient parallelization of checks: (1) speculative variables,
and (2) the ability to add checks by static instrumentation
the runtime penalties of compiler generated runtime checks. An obvious
approach is to use idle cores of modern multi-core CPUs to parallelize
the runtime checks. This could be accomplished by (a) parallelizing the
application and in this way, implicitly parallelizing the checks, or (b) by
parallelizing the checks only. Parallelizing an application is rarely easy
and frameworks that simplify the parallelization, e.g., like software trans-
actional memory (STM), can introduce considerable overhead. ParExC is
based on alternative (b). We compare it with an approach using a trans-
actional memory-based alternative. Our experience shows that ParExC
is not only more efficient than the STM-based solution but the manual
effort for an application developer to integrate ParExC is lower. ParExC
has – in contrast to similar frameworks – two noteworthy features that
permit a more efficient parallelization of checks: (1) speculative variables,
and (2) the ability to add checks by static instrumentation
Details
Original language | English |
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Pages | 698-710 |
Number of pages | 13 |
Publication status | Published - 2009 |
Peer-reviewed | Yes |
Conference
Title | SSS '09: 11th International Symposium on Stabilization, Safety, and Security of Distributed Systems, Springer-Verlag, 2009. |
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Abbreviated title | SSS '09 |
Conference number | |
Duration | 3 November 2009 |
Degree of recognition | International event |
Location | |
City | Lyon |
Country | France |
External IDs
Scopus | 70549093026 |
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Keywords
Research priority areas of TU Dresden
DFG Classification of Subject Areas according to Review Boards
Keywords
- Speculative variable, Transactional memory, Static instrumentation, Shared View, Taint Analysis