Smoothing Disruption Across the Stack: Tales of Memory, Heterogeneity, & Compilers

Research output: Contribution to book/Conference proceedings/Anthology/ReportConference contributionContributedpeer-review

Contributors

Abstract

Multiple research vectors represent possible paths to improved energy and performance metrics at the application-level. There are active efforts with respect to emerging logic devices, new memory technologies, novel interconnects, and heterogeneous integration architectures. Of great interest is quantifying the potential impact of a given solution to prioritize research vectors accordingly. In this paper, we discuss two efforts - one focused on emerging memory technology, and another focused on heterogeneous integration technology - that speak to best practices for, and needed contributions from the design automation (DA) community to explore this vast design space. Furthermore, we highlight new research efforts that aim to develop the novel compiler abstractions and frameworks that are ultimately needed to derive maximum value from new memory and/or heterogeneous and monolithic integration architecture, and that can also play an important role with respect to design space exploration efforts.

Details

Original languageEnglish
Title of host publication2024 Design, Automation and Test in Europe Conference and Exhibition, DATE 2024 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
ISBN (electronic)9798350348590
Publication statusPublished - 2024
Peer-reviewedYes

Publication series

SeriesProceedings -Design, Automation and Test in Europe, DATE
ISSN1530-1591

Conference

Title2024 Design, Automation and Test in Europe Conference and Exhibition
Abbreviated titleDATE 2024
Conference number27
Duration25 - 27 March 2024
Website
LocationPalacio De Congresos De Valencia
CityValencia
CountrySpain

External IDs

ORCID /0000-0002-5007-445X/work/173985260
ORCID /0000-0001-9295-3519/work/191041736

Keywords

ASJC Scopus subject areas

Keywords

  • associative memory, chiplet, compilers, Compute-in-memory, cross-bar architectures, distance functions, ferroelectric field effect transistors (FeFETs), heterogeneous integration, pathfinding