SIListra Compiler: Building Reliable Systems with Unreliable Hardware (Poster paper)
Research output: Contribution to book/Conference proceedings/Anthology/Report › Conference contribution › Contributed › peer-review
Contributors
Abstract
On one hand, hardware is expected to become
more unreliable in future. On the other hand, more and more
applications become safety critical, i.e., rely on the correct
function of the underlying hardware. To close this gap we pro-
pose to add error detection capabilities to the application with
our SIListra Compiler. Our compiler automatically transforms
C applications based on the well-known principle of Coded
Processing. Our evaluation demonstrates that applications
compiled with our SIListra Compiler reliably detect hardware
errors as requested by various safety standards (such as ISO
26262).
more unreliable in future. On the other hand, more and more
applications become safety critical, i.e., rely on the correct
function of the underlying hardware. To close this gap we pro-
pose to add error detection capabilities to the application with
our SIListra Compiler. Our compiler automatically transforms
C applications based on the well-known principle of Coded
Processing. Our evaluation demonstrates that applications
compiled with our SIListra Compiler reliably detect hardware
errors as requested by various safety standards (such as ISO
26262).
Details
| Original language | English |
|---|---|
| Title of host publication | Proceedings of The 41st Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2011) |
| Number of pages | 4 |
| Publication status | Published - 2011 |
| Peer-reviewed | Yes |
Keywords
Research priority areas of TU Dresden
DFG Classification of Subject Areas according to Review Boards
Keywords
- coded processing, Failure detection, hardware reliability, arithmetic code