Since dynamic power has a quadratic relationship with voltage, reducing voltage is an effective way to lower power consumption in digital circuits. However, maintaining stable operation at lower voltages is challenging due to increased sensitivity to process, voltage, and temperature (PVT) variations, making it difficult to determine optimal operating points using static timing analysis (STA). While circuit- and device-level solutions like timing error detection (TED) systems can enable lower voltage operation, they introduce significant overhead and design complexity. In this article, we integrate an algorithm-based fault tolerance (ABFT) method into the structure of systolic arrays (SAs) to capture timing errors when voltage is scaled down, ensuring safe and optimized low-voltage operation. Our proposed approach, SCISSORS, demonstrates how extra voltage margins in SAs used for matrix arithmetic can be trimmed by integrating a simple algorithmic technique into the structure of the array. This solution not only detects errors in the accelerator but also those caused by voltage reduction in on-chip memory and auxiliary circuits. It is fully implementable through hardware description languages (HDL) without requiring transistor- or circuit-level modifications to the netlist. Implementation on a Zynq system-on-chip (SoC) shows that SCISSORS introduces only a tolerable overhead of 11% and 8% for 32×32 and 64×64 SAs, respectively, while achieving nearly a 2× improvement in energy efficiency. Experimental results further demonstrate that SCISSORS adaptively adjusts voltage in response to the voltage-temperature coupling behavior of digital circuits at runtime, specifically addressing inverse temperature dependence (ITD).