FPGA virtualization allows the shared usage of an FPGA by several operating systems with different criticality levels. To avoid mutual interference, most state-of-the-art systems strictly isolate subsystems in spatial respect at the expense of lower resource utilization. We present an allocation and scheduling strategy for hardware tasks that improves resource utilization while respecting different real-time levels (hard, soft, and no real-time) of guest operating systems. To not jeopardize deadlines, Dynamic Partial Reconfiguration (DPR) latencies are reduced by reusing, prefetching and reserving of hardware accelerators. Compared with an existing scheduler for hardware tasks, we could increase the resource usage by 156% while deadline misses were reduced by 6%.