While the footprint of digital cmos circuits has continued to decrease over the years, physical limitations for further intra-layer geometric scaling become apparent. To further increase the logic density, the international roadmap for devices and systems (irds) predicts a transition from a single layer of transistors per die to monolithically stacking transistors in multiple tiers starting from 2031. This raises the question of the extent to which these can be exploited in 3D standard cells to improve logic density. In this work, we investigate the scaling potential of realizing standard cells employing 2 or 3 dedicated tiers. For this, specific multi-tier virtual physical design kits are derived based on the open ASAP7. A typical RISC-V implementation realized in a classic standard cell library is used to identify the subset of most relevant standard cells. In accordance with the virtual PDK, 3D derivatives of the single tier standard cells are crafted and evaluated with respect to achievable logic density considering standard synthesis benchmarks and block on architecture level.