RTSim: A Cycle-Accurate Simulator for Racetrack Memories

Research output: Contribution to journalResearch articleContributedpeer-review



Racetrack memories (RTMs) have drawn considerable attention from computer architects of late. Owing to the ultra-high capacity and comparable access latency to SRAM, RTMs are promising candidates to revolutionize the memory subsystem. In order to evaluate their performance and suitability at various levels in the memory hierarchy, it is crucial to have RTM-specific simulation tools that accurately model their behavior and enable exhaustive design space exploration. To this end, we propose RTSim, an open source cycle-accurate memory simulator that enables performance evaluation of the domain-wall-based racetrack memories. The skyrmions-based RTMs can also be modeled with RTSim because they are architecturally similar to domain-wall-based RTMs. RTSim is developed in collaboration with physicists and computer scientists. It accurately models RTM-specific shift operations, access ports management and the sequence of memory commands beside handling the routine read/write operations. RTSim is built on top of NVMain2.0, offering larger design space for exploration.


Original languageEnglish
Article number8642352
Pages (from-to)43-46
Number of pages4
JournalIEEE computer architecture letters
Issue number1
Publication statusPublished - 1 Jun 2019

External IDs

ORCID /0000-0002-5007-445X/work/141545543


Research priority areas of TU Dresden

ASJC Scopus subject areas


  • cache, domain wall memory, emerging memory technologies, main memory, Memory simulator, memory system, NVM, racetrack memory, scratchpad, simulation

Library keywords