The electrical behavior of lateral 4H-SiC n-laterally-diffused metal-oxide semiconductor (LDMOS) transistors with reduced surface field (RESURF) for integrated circuits was designed, measured, and modeled using different design variations. An additional implanted n-layer forming the drift region of the device in a p-doped epitaxy promotes a RESURF and thereby enhances the breakdown capability. The design rules of the presented power MOSFET are compatible to an existing technology for a novel 20-V 4H-SiC CMOS process. The dose of the additionally implanted RESURF region with a depth of approximately 390 nm was 3.5·1012 cm-2. Breakdown voltages in the range of 372-981 V and ON-state resistances from 1000 down to 54 mQ cm2 were measured, depending on the design variations. The best measured figure-of-merit (FOM, V2BD/RON) value results in 12.3 MW/cm2. Additionally, the electrical behavior of the presented n-LDMOS transistor was compared to a TCAD simulation model. Hereby, design guidelines concerningthe length of the channel, drift region, and field plate were derived, which will be helpful for further investigations. Moreover, according to the simulations, a deeper RESURF region of 1 μm and a higher RESURF dose of 6·1012 cm-2 would even result in FOM values above 43 MW/cm2.