Resource-Efficient FPGA-based I/Q-Demodulator Detects 0.0005 Modulation Index with 9.5 dB SNR for Converse ME Sensors
Research output: Contribution to book/Conference proceedings/Anthology/Report › Conference contribution › Contributed › peer-review
Contributors
Abstract
This paper presents the design and implementation of a resource-efficient FPGA-based system for real-time demodulating and processing signals of Converse-Magnetoelectric (C-ME) sensors. This particular ME sensor type, also known as electrically modulated ME sensors, combining a piezoelectric resonator with a magnetostrictive layer, generates a DoubleSideband Amplitude Modulation with Carrier signal when excited at their resonance frequency defined by the sensor dimension. We simulate the implementation of an in-phase and quadrature (I/Q)-Demodulation approach to address phase shift challenges arising from unsynchronized excitation sources. This enables accurate recovery of the magnetic signal from the sensor’s signal envelope. We designed the system using a CORDIC-based numerically controlled oscillator for flexible carrier frequency generation and a cascaded integrator-comb filter for efficient decimation and noise reduction. Resource-sharing techniques in FIR low-pass filtering and a non-restoration square root algorithm were employed to maximize FPGA resource efficiency. The final processing stage includes DC offset removal to ensure accurate magnetic signal recovery at baseband. Simulation results assuming an ideal C-ME signal after the Analog-to-Digital Converter confirms that the system accurately demodulates the desired to-be-measured signal with a modulation index of at least 0.0005, giving an output signal-to-noise ratio of 9.5 dB at a sampling frequency of 1 MSa/s. This modulation index corresponds to the detection limit (equals three times the estimated noise amplitude spectral density), considering the C-ME sensor’s ultra-low noise spectral density and the signal conditioning and quantization noise contributions. The resource efficiency of the design allows future integrations and optimization of digital signal processing algorithms for further signal-to-ratio enhancing performance.
Details
| Original language | English |
|---|---|
| Title of host publication | 2024 IEEE 42nd Central America and Panama Convention (CONCAPAN XLII) |
| Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| Number of pages | 6 |
| ISBN (electronic) | 979-8-3503-6672-3 |
| ISBN (print) | 979-8-3503-6673-0 |
| Publication status | Published - 29 Nov 2024 |
| Peer-reviewed | Yes |
Conference
| Title | 2024 IEEE 42nd Central America and Panama Convention |
|---|---|
| Abbreviated title | CONCAPAN XLII |
| Conference number | 42 |
| Duration | 27 - 29 November 2024 |
| Website | |
| Location | Hotel Crowne Plaza San José, La Sabana |
| City | San José |
| Country | Costa Rica |
External IDs
| ORCID | /0000-0001-8012-6794/work/184006560 |
|---|---|
| Scopus | 105005839490 |
Keywords
Sustainable Development Goals
ASJC Scopus subject areas
Keywords
- Amplitude Modulation (AM), CIC (Cascaded-Integrator-Comb-Filter) Filter, CORDIC, Demodulation, FIR Filter, FPGA, In-Phase and Quadrature (I/Q), Medical Real-Time Signal Processing, Numerically Controlled Oscillator (NCO)