RePaBit: Automated generation of relocatable partial bitstreams for Xilinx Zynq FPGAs

Research output: Contribution to book/Conference proceedings/Anthology/ReportConference contributionContributedpeer-review

Contributors

  • Jens Rettkowski - , Ruhr University Bochum (Author)
  • Konstantin Friesen - , Ruhr University Bochum (Author)
  • Diana Gohringer - , Ruhr University Bochum (Author)

Abstract

Partial reconfiguration in FPGAs increases the flexibility of a system due to dynamic replacement of hardware modules. However, more memory is needed to store all partial bitstreams and the generation of all partial bitstreams for all possible regions on the FPGA is very time-consuming. In order to overcome these issues, bitstream relocation can be used. In this paper, a novel approach that facilitates bitstream relocation with the Xilinx Vivado tool flow is presented. In addition, the approach is automated by TCL scripts that extend Vivado to RePaBit. RePaBit is successfully evaluated on the Xilinx Zynq FPGA using 1D and 2D relocation of complex modules such as MicroBlaze processors. The results show a negligible overhead in terms of area and frequency while enabling more flexibility by partial bitstream relocation as well as a faster design time.

Details

Original languageEnglish
Title of host publication2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2016
EditorsPeter Athanas, Rene Cumplido, Claudia Feregrino, Ron Sass
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (electronic)9781509037070
Publication statusPublished - 2016
Peer-reviewedYes
Externally publishedYes

Publication series

SeriesInternational Conference on Reconfigurable Computing and FPGAs (ReConFig)

Conference

Title2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2016
Duration30 November - 2 December 2016
CityCancun
CountryMexico

External IDs

ORCID /0000-0003-2571-8441/work/159607574

Keywords

Keywords

  • FPGA, Isolation Design Flow, Partial Bitstream, Partial Reconfiguration, Relocation, Xilinx Vivado, Xilinx Zynq