RECON: Resource-Efficient CORDIC-Based Neuron Architecture.

Research output: Contribution to journalResearch articleContributedpeer-review

Contributors

Abstract

Contemporary hardware implementations of artificial neural networks face the burden of excess area requirement due to resource-intensive elements such as multiplier and non-linear activation functions. The present work addresses this challenge by proposing a resource-efficient Co-ordinate Rotation Digital Computer (CORDIC)-based neuron architecture (RECON) which can be configured to compute both multiply-accumulate (MAC) and non-linear activation function (AF) operations. The CORDIC-based architecture uses linear and trigonometric relationships to realize MAC and AF operations respectively. The proposed design is synthesized and verified at 45nm technology using Cadence Virtuoso for all physical parameters. Implementation of the signed fixed-point 8-bit MAC using our design, shows 60% less area, latency, and power product (ALP) and shows improvement by 38% in area, 27% in power dissipation, and 15% in latency with respect to the state-of-the-art MAC design. Further, Monte-Carlo simulations for process-variations and device-mismatch are performed for both the proposed model and the state-of-the-art to evaluate expectations of functions of randomness in dynamic power variation. The dynamic power variation for our design shows that worst-case mean is 189.73 μ W which is 63% of the state-of-the-art.

Details

Original languageEnglish
Article number9335308
Pages (from-to)170-181
Number of pages12
JournalIEEE Open Journal of Circuits and Systems
Volume2
Publication statusPublished - 2021
Peer-reviewedYes

External IDs

Scopus 85106627255

Keywords

Research priority areas of TU Dresden

Keywords

  • AF, configurable architecture, CORDIC, MAC, neural network