The evolution of 5G New Radio (NR) increases the demand for flexible, portable, software-based baseband processing on programmable platforms. However, current solutions are still largely based on highly specialized DSPs or FPGAs, which often require dedicated tool flows and offer limited portability. The recently ratified RISC-V vector extension (RVV 1.0) provides an open-standard vector ISA that may address these limitations. Still, its suitability for wireless baseband workloads remains unclear due to the absence of DSP-specific and complexarithmetic instructions. This paper investigates the feasibility of implementing an MMSE-based MIMO equalizer for OFDM systems using standard RVV 1.0 instructions and 32-bit fixedpoint arithmetic. We present a methodology that combines BER (Bit Error Rate)-driven precision selection, subcarrier-parallel vectorization, register-pressure management, and instruction rescheduling. Using a 4 4 OFDM-MIMO system as a case study, our implementation on Saturn with VLEN = 4096 bits and DLEN = 512 bits/cycle achieves a 100 speedup over its scalar baseline and a throughput of 28.05 cycles per symbol while maintaining BER performance comparable to the floating-point reference under the evaluated conditions. We further estimate the processor-frequency requirements for representative LTE and 5G scenarios and compare the results across the RVV processors Ara2 and Saturn. The study identifies both the capabilities and the limitations of standard RVV 1.0 for wireless baseband processing and highlights promising directions for future ISA and microarchitectural enhancements.