Because of economic pressure, more commodity hardware
with insufficient error detection is used in critical applications. More-
over, it is expected that commodity hardware is becoming less reliable
because of the continuously decreasing feature size. Thus, we expect that
software-implemented approaches to deal with unreliable hardware will
be needed. Arithmetic codes are well suited for this purpose because they
can provide very good error detection capabilities independent of the ac-
tual failure modes of the underlying hardware. But arithmetic codes gen-
erate high slowdowns. This paper describes our encoding which uses an
expensive AN-code. Second, we show how we harness the power of mod-
ern multicore CPUs to parallelize this expensive but flexible and power-
ful software-implemented fault detection technique. Our measurements
show that under continuous probabilistic error injection, AN-encoding
reduces the number of runs with incorrect output from 15.9% for the
unencoded execution to 0.5% in the encoded case. Our parallelization
reduces the observed slowdowns by an order of magnitude.