To meet response time and throughput demands, data processing architects continuously adapt query processing systems to novel hardware features. For instance, data processing systems already shifted from disk-oriented to main memory-oriented architectures to efficiently exploit the ever-increasing capacities of main memory. A prominent example for such new developments are emerging memory technologies such as very large caches, high-bandwidth memory (HBM), non-uniform memory access (NUMA) or remote-memory designs like CXL. These memories complement regular DRAM by trading off between properties such as capacity, read/write throughput or access latency. However, these degrees of freedom and their inherent complexity make it difficult for database systems to profit from the new hardware. Taking HBM – as integrated in the 2023 Intel “Sapphire Rapids” Xeon Max processors – as a most recent example for emerging memory technologies, we present results from microbenchmarks that demonstrate different worker-thread saturation patterns for DRAM and HBM in this paper. Then, we subsequently derive characteristics and a cost model to make dynamic on-the-fly data-distribution/movement decisions. Based on this model, we show that for data processing queries with a specific data-reuse pattern, dynamic data (re-)distribution from DRAM to HBM can decrease end-to-end query run times.