On-line Analysis of Hardware Performance Events for Workload Characterization and Processor Frequency Scaling Decisions

Research output: Contribution to book/conference proceedings/anthology/reportConference contributionContributedpeer-review

Abstract

Energy efficiency optimizations of computational resources continue to be of growing importance for both classical datacenter workloads as well as high performance computing environments. New hardware generations introduce more and more energy efficiency features, resulting in a power consumption variation by at least a factor of four between idle and full load. Even the power consumption of different full-load workloads can vary substantially, clearly showing that there is energy saving potential apart from the traditional “race to idle”. In this paper we present a configurable CPU frequency governor that adapts processor frequencies based on performance counter measurements instead of processor load. We use the SPEC OMP benchmark suite to determine the potential of our approach and present governor configurations for two up-to-date x86 64 microarchitectures. Moreover we show that substantial follow-up work is required to assess further efficiency optimization potential in this field.

Details

Original languageEnglish
Title of host publicationProceeding of the second joint WOSP/SIPEW international conference on Performance engineering
Place of PublicationNew York, NY, USA
PublisherAssociation for Computing Machinery (ACM), New York
Pages481-486
Number of pages6
ISBN (Print)978-1-4503-0519-8
Publication statusPublished - 2011
Peer-reviewedYes

Conference

TitleInternational Conference on Performance Engineering
Abbreviated titleICPE
Conference number2
Duration14 - 16 March 2011
Website
Degree of recognitionInternational event
Location
CityKarlsruhe
CountryGermany

External IDs

Scopus 79953872146
ORCID /0000-0002-8491-770X/work/141543301

Keywords

Sustainable Development Goals

Keywords

  • dvfs, energy efficiency, frequency governor, performance counter