We report on the multi-level-cell (MLC) operation of AND-connected ferroelectric FET (FeFET) arrays and their suitability for Compute-in-Memory (CiM) applications. The switching behavior and device variation of FeFETs in a passive AND array test-structure configuration is investigated. From this, we derive suitable write schemes and inhibit schemes capable of protecting any FeFET state. This enables the MLC operation of the AND arrays, yielding a performance suitable for CiM applications. We investigate the impact of the obtained bit-error-rate (BER) of 4% in inference-only operation, which shows only a 1% degradation from the floating-point (FP) accuracy for CIFAR-10 datasets with LeNET.