MoSim: A Modular Simulation Framework for FPGA-based Systolic CNN Accelerators
Research output: Contribution to book/Conference proceedings/Anthology/Report › Conference contribution › Contributed › peer-review
Contributors
Abstract
Architectural simulators are widely used in computer architecture to explore design spaces and validate ideas before implementation. Recent works such as Scale-Sim extend this approach to convolutional neural network (CNN) accelerators, particularly systolic array-based designs. However, most target ASIC and overlook the unique resource characteristics of FPGA which is now a popular platform for CNN acceleration. To address this gap, we present MoSim, a modular, cycle-accurate simulator tailored for FPGA-based systolic CNN accelerators. MoSim models FPGA-specific resources and reports detailed performance and resource statistics to facilitate design space exploration. Evaluations on representative CNN workloads demonstrate that the simulator effectively captures FPGA-specific effects and guides practical design decisions.
Details
| Original language | English |
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| Title of host publication | ISCAS 2026 - 2026 IEEE International Symposium on Circuits and Systems |
| Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| Pages | 773-777 |
| Number of pages | 5 |
| ISBN (electronic) | 979-8-3315-7769-8 |
| ISBN (print) | 979-8-3315-7770-4 |
| Publication status | Published - 18 Jun 2026 |
| Peer-reviewed | Yes |
Publication series
| Series | Proceedings - IEEE International Symposium on Circuits and Systems |
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| ISSN | 0271-4310 |
Conference
| Title | IEEE International Symposium on Circuits and Systems 2026 |
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| Subtitle | Circuits and Systems for Intelligent Society |
| Abbreviated title | ISCAS 2026 |
| Duration | 24 - 27 May 2026 |
| Website | |
| Location | Shanghai International Convention Center |
| City | Shanghai |
| Country | China |
External IDs
| ORCID | /0000-0003-2571-8441/work/222760616 |
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Keywords
ASJC Scopus subject areas
Keywords
- Architectural Simulator, FPGA, Systolic Array