Monitoring cache behavior on parallel SMP architectures and related programming tools

Research output: Contribution to journalResearch articleContributedpeer-review



This paper describes the ideas and developments of the project EP-CACHE. Within this project new methods and tools are developed to improve the analysis and the optimization of programs for cache architectures, especially for SMP clusters. The tool set comprises the semi-automatic instrumentation of user programs, the monitoring of the cache behavior, the visualization of the measured data, and optimization techniques for improving the user program for better cache usage.

As current hardware performance counters do not give sufficient user relevant information, new hardware monitors are designed that provide more detailed information about the cache utilization related to the data structures and code blocks in the user program. The expense of the hardware and software realization will be assessed to minimize the risk of a real implementation of the investigated monitors. The usefulness of the hardware monitors is evaluated by a cache simulator. (c) 2004 Published by Elsevier B.V.


Original languageEnglish
Pages (from-to)1298-1311
Number of pages14
JournalFuture Generation Computer Systems
Issue number8
Publication statusPublished - Oct 2005


TitleEuropean Grid Conference
Duration14 - 16 February 2005

External IDs

Scopus 24044464525
WOS 000231859800007


DFG Classification of Subject Areas according to Review Boards


  • hardware cache monitoring, performance analysis, cache optimizations, parallel programming tools, SMP cluster