In this work, we leverage ambipolar transistors in the context of metastability for random number generation. We propose designs of a Minority-based SR latch and a dual-edge triggered True Single Phase Clock D-Flip-Flop (TSPC DFF) to sample two random bits in a single clock cycle. We demonstrate how metastable circuits based on ambipolar transistors allow doubling the throughput as compared to a similar standard CMOS-based design. The proposed design is compact in terms of the number of transistors per block (60% less transistors), power consumption (saving 94.5% leakage power and 70.7% dynamic power) and path delay (77.3% reduction) with respect to its CMOS counterpart.