Processing-in-Memory (PIM) architectures enable computation directly within DRAM and help combat the memory wall problem. While commodity DRAM has been demonstrated for data movement and bulk-bitwise PIM, data must be reorganized away from row-wise ordering and byte addressability used by typical processors into a column-ordering where bytes and words are spread across rows within a single column since there is no mechanism to move data between bitlines which is required for many computational operations including addition and multiplication. In this paper, we propose a DRAM subarray design that enables in-DRAM bit-shifting for open-bitline architectures. By adding migration cells at the top and bottom of each subarray, bidirectional bit-shifting may be conducted within any given row. In this paper we present initial findings and evaluation of potential timing and energy analysis using a combination of approaches from VLSI layout, spice simulation and demonstrate integration into NVMain-PIM a simulator extended with DRAM PIM primitives.