Low Power Scheduling of Periodic Hardware Tasks in Flash-Based FPGAs
Research output: Contribution to conferences › Paper › Contributed › peer-review
Contributors
Abstract
Flash-based FPGAs are well suited for energy aware applica-tions because they are liable to a much lower static energy consumption than SRAM-based FPGAs. The power consump-tion of Microsemi / Microchip devices is reduced even further due to a low-power mode called Flash*Freeze. Nevertheless, when many hardware tasks with different idle times share the same FPGA, the applicability of the Flash*Freeze mode is re-duced as only the complete FPGA can be put into Flash*Freeze mode. In this paper, a scheduling algorithm called cluster scheduling is introduced that reduces the power consumption by clustering periodic hardware tasks and extending Flash*Freeze periods under consideration of real-time con-straints. The cluster scheduling algorithm can run standalone or it can be integrated into a real-time operating system. It is evaluated against an algorithm that switches to Flash*Freeze mode whenever the FPGA is idle. Depending on the shifting variability of the hardware tasks, a prolongation of the Flash*Freeze mode in the order of n can be reached with n given hardware tasks.
Details
Original language | English |
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Publication status | Published - 2020 |
Peer-reviewed | Yes |
External IDs
Scopus | 85099783218 |
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ORCID | /0000-0003-2571-8441/work/142240481 |
Keywords
Sustainable Development Goals
Keywords
- Low Power