The design methodology of low power current mode logic (CML) latches is described and the implementation of a D flip-flop (DFF) is presented in 28 nm CMOS technology. The DFF can work up to 22 Gbps full-rate with a bit error rate better than 10-12 and with a power consumption of only 880 μW. Since the circuit is inductor-less the area of the circuit is only 25 μm × 10 μm. As a further implementation of the CML latches a very low power static frequency divider with quadrature outputs in 28 nm is presented. It divides the clock signal up to 26 GHz and has only 880 μW power consumption. To our knowledge, with 0.034 mW/GHz, this static frequency divider has one of the best figure of merit reported to date.