Logic architecture and VDD selection for reducing the impact of intra-die random Vt variations on timing

Research output: Contribution to book/Conference proceedings/Anthology/ReportConference contributionContributedpeer-review

Contributors

  • Bahman Kheradmand-Boroujeni - , Swiss Center for Electronics and Microtechnology (CSEM), Swiss Federal Institute of Technology Lausanne (EPFL) (Author)
  • Christian Piguet - , Swiss Center for Electronics and Microtechnology (CSEM) (Author)
  • Yusuf Leblebici - , Swiss Federal Institute of Technology Lausanne (EPFL) (Author)

Abstract

We show that in logic circuits working at supply voltage (VDD) below nominal value, proper selection of logic architecture and VDD together can reduce the impact of device-to-device random process variations (PV) on timing. First we show that σ/μ of transistor current and delay strongly depend on VDD. Then we compare the PV sensitivity of Low-Power Slow (LP-S) and High-Power Fast (HP-F) architectures. The results propose the idea that for a given technology, equal power budget and delay, LP-S circuits working at higher VDD are about 1.8X less PV sensitive compare to HP-F circuits working at lower VDD.

Details

Original languageEnglish
Title of host publicationLecture Notes in Computer Science
PublisherSpringer, Berlin, Heidelberg
Pages170-179
Number of pages10
Volume6448
ISBN (electronic)978-3-642-17752-1
ISBN (print)978-3-642-17751-4
Publication statusPublished - Sept 2011
Peer-reviewedYes
Externally publishedYes

Workshop

Title20th International Workshop on Power and Timing Modeling, Optimization and Simulation 2010
Abbreviated titlePATMOS 2010
Conference number20
Duration7 - 10 September 2010
CityGrenoble
CountryFrance

External IDs

Scopus 85037546282

Keywords