Improving autonomous soft-error tolerance of FPGA through LUT configuration bit manipulation.
Research output: Contribution to book/Conference proceedings/Anthology/Report › Conference contribution › Contributed › peer-review
Contributors
Details
Original language | Undefined |
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Title of host publication | FPL |
Pages | 1-8 |
Number of pages | 8 |
Publication status | Published - 2013 |
Peer-reviewed | Yes |
Externally published | Yes |
External IDs
Scopus | 84898634087 |
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