Sharing tightly coupled memories (TCMs) is popular in embedded multi-processor systems-on-a-chip (MPSoCs) to improve hardware efficiency and software flexibility. The obligatory access conflict resolution logic may be detrimental to the system’s critical path and therefore the performance. Access interval prediction (AIP) mitigates this degradation by enabling offline arbitration. A couple of AIP algorithms have been presented, some reaching accuracies of over $97 \%$. This paper presents the first register-transfer level (RTL) implementation of one of these—the tagged geometric history length access interval predictor (TAGE-AIP). We present two predictor variants, one with a clock frequency of 600 MHz and an accuracy of $97.1 \%$ and a smaller reduced variant running at 625 MHz with 96.9 % accuracy. The prediction and update procedures fit in the given time budget in both variants. We analyze the area and the timing of the design and how it is influenced by the design parameters.