Improving energy efficiency is most likely one of the key challenges we face for the years to come. The ever increasing energy demand, at the moment exponentially growing for information and communication technology, leads to growing emissions of greenhouse gases, that will with very high probability alter our climate.

In order to maintain the level of ubiquitous available communication services and instead even increase data transmission rates for a growing number of users, the underlying hardware has to become significantly more energy efficient to limit the high energy consumption. Besides this climate awareness rationale, in particular the wireless communication sector drives towards higher energy efficiency simply to increase the battery lifetime of mobile devices, covering more and more different communication standards for ever increasing integrated functionality.

Nowadays the dominating IC technology is CMOS. It offers excellent properties for digital circuitry as low standby currents and highest integration density, achieved by the long standing quest for shrinking structure size as predicted by Moore’s law. Cost efficiency is the main driver behind the goal to integrate digital baseband and analog RF frontend into one CMOS IC. Unfortunately, the CMOS characteristics are less adapted to the needs of analog ICs, which applies in particular for CMOS power amplifier (PA) design, the topic of this work.

Looking at the challenge a PA designer faces explains this. It is characterized by the need to simultaneously maximize the key figures of merit efficiency, output power, linearity, stability, RF gain and matching, being intrinsically interconnected. Scaled CMOS technology as the 180 nm process used in this work, offers the essential high transit frequency to achieve high RF gain, but inflicts serious drawbacks. The metal layers used to integrate passive components are scaled accordingly, which reduces the distance to the lossy silicon substrate and thereby increases the capacatively coupled RF power loss into it. Moreover, the transistor break down voltages decrease due to the aggressively scaled gate lengths, reducing the applicable supply voltages. This decreases the achievable output power, depending quadratically on the supply voltage. The saturation voltage, however, reduces only marginally, which as a consequence, lessens the available RF swing in relation to the supply voltage, and hence the efficiency.

Dedicated highly optimized architectures are necessary to overcome the hurdles that arise with the use of CMOS in order to achieve figures of merit (FOM) that can compete with circuit implementations based on SiGe HBTs. Intendend for the WLAN and Bluetooth standard in the S- and C-band, several architectures are implemented and measured, allowing to compare the FOM and draw conclusions concerning their suitability for the different applications areas. The research is carried out in the framework of the EU funded RESOLUTION project, which aims at developing a 3D local positioning system with cm accuracy. The achievements, which are published in leading international journal and conference contributions, comprise:

A 5 GHz - 6 GHz class AB PA with η η of 28.1% and P_1dB of 19.8 dBm for a Vdd} of 1.9 V, measured at 5.5 GHz. The design process and the load pull analysis is presented.

A 5 GHz - 7 GHz dual stage class AB PA with η of 19.0% and P_1dB of 18.5 dBm for a Vdd of 1.9 V, measured at 5.8 GHz. Included are RF system related design choices as DC and RF switch. The measurements of wafer probed die versus wire bonded and packaged solution are examined in detail.

A 5 GHz - 6 GHz class F 3rd order harmonic resonator PA with η up to 52.0% and P_1dB of 16.2 dBm for a Vdd} of 1.5 V at 5.5 GHz. For a Vdd of 1.9 V, η above 50% and P_1dB of 18.4 dBm are measured.

A 1 GHz - 8 GHz TWA with η of 17.7% and P_1dB of 16.1 dBm for a Vdd of 2.4 V, measured at 2.4 GHz. At 5.5 GHz, a measured η of 15.8% and a P_1dB of 16.6 dBm is achieved. The existing TWA theory is enhanced by taking the significant parasitic inductor losses into account, allowing an enhanced RF gain prediction accuracy.

A 2 GHz - 9 GHz tapered TWA with excellent η of 33.9% and P_1dB of 16.2 dBm for a Vdd of 2.4 V, measured at 2.4 GHz. At 5.5 GHz, a η of 33.4% and a P_1dB of 18.5 dBm is measured. The detailed circuit analysis derives optimization methods for tapered TWA structures and explain the fundamental working principle.

The results obtained are among the best of current state-of-the-art CMOS power amplifiers, partially approaching the performance of SiGe HBT based circuits in terms of drain efficiency as for example with the class F PA or the tapered TWA. Although performances based on III/V technology most often outperform CMOS implementations, the circuits presented here definitely reduce this gap and lead to highly cost competitive implementations. The state-of-the-art theory of TWAs is enhanced by a more accurate RF gain model incorporating the integrated inductor losses. The extensive tapered TWA analysis by means of a dedicated small signal model enables to derive the design constraints for an optimized implementation.