Hardware-Level Adaptive Scheduling for Reconfigurable Accelerators on Virtualized FPGAs

Research output: Contribution to book/Conference proceedings/Anthology/ReportConference contributionContributedpeer-review

Abstract

Robot systems are facing a growing demand for realtime performance of multiple computing tasks and autonomous decision-making. However, limited computing resources make efficient scheduling of computing tasks and optimizing resource utilization a key challenge. Virtualization of field-programmable gate arrays enables the dynamic sharing of hardware resources, while dynamic partial reconfiguration allows for flexible adjustment of hardware accelerators based on task requirements, making it suitable for complex and fluctuating computing loads. However, virtualization scheduling based on operating systems or microkernels usually introduces high software overhead. This paper proposes a hardware-level adaptive scheduling mechanism integrated with spatiotemporal scheduling to efficiently share reconfigurable computing resources among multiple users. This mechanism is transparent to users and can adaptively adjust the spatiotemporal allocation strategy according to the characteristics of tasks. In addition, the scheduling scheme introduces access rights management to strictly prevent unauthorized resource access. Hardware scheduling system achieves a speedup of over 1000 × compared to a software-based scheduling system when executing 100 hardware tasks, reducing execution time from seconds to milliseconds.

Details

Original languageEnglish
Title of host publication2025 28th Euromicro Conference on Digital System Design (DSD)
EditorsDaniel Casini, Francisco J. Cazorla
PublisherIEEE Canada
Pages566-573
Number of pages8
ISBN (electronic)979-8-3315-8499-3
ISBN (print)979-8-3315-8500-6
Publication statusPublished - 12 Sept 2025
Peer-reviewedYes

Publication series

SeriesEuromicro Symposium on Digital System Design (DSD)
ISSN2639-3859

Conference

Title28th Euromicro Conference on Digital System Design
Abbreviated titleDSD 2025
Conference number28
Duration10 - 12 September 2025
Website
LocationGrand Hotel
CitySalerno
CountryItaly

External IDs

ORCID /0000-0003-2571-8441/work/203068523
Scopus 105030537791

Keywords

Keywords

  • Adaptive scheduling, Dynamic scheduling, Field programmable gate arrays, Hardware, Permission, Processor scheduling, Resource management, Software, Spatiotemporal phenomena, Virtualization, Dynamic partial reconfiguration, FPGA virtualization, Hardware scheduler