Tactile Internet (TI) applications such as industry automation, connected autonomous cars, augmented reality and remote surgery, are based on secure data transmissions at a very low end-to-end latency. In order to fulfill those requirements in real applications, it is necessary to implement traffic encryption when data flows at higher communication protocol layers. Nevertheless, the implementation of the aforementioned protocols is a computing intensive task, in which many arithmetic operations are involved, leading to considerable delay. Therefore, hardware acceleration may be a solution to reduce the overall computing time, while delivering enough throughput during the execution of the network security functions. In this paper, we implement hardware accelerators for cryptographic algorithms on heterogeneous multi-core dedicated hardware, using state-of-the-art embedded libraries, cryptographic cores and hardware extensions. By comparing our implementation to software-only solutions in terms of latency and throughput using variable data sets, we find latency reductions in the computing time around 80% as well as performance improvements up to three orders of magnitude.