The interplay of alternative materials, large-scale integration technologies, and innovative devices plays a pivotal role on the way to fault-tolerant quantum computing. In this context, gate-controlled superconductivity (GCS) emerges as a key enabling technology, promising to advance superconducting logic and quantum electronics, complementing conventional approaches based on Josephson effects and quantum interference. Here, we demonstrate all-metallic superconducting ZrN nanostructures on silicon, fabricated entirely using a subtractive, monolithic dry-etch approach with a 300 mm CMOS-compatible process flow. For Dayem-bridge weak links with decreasing width down to 27 nm, we observe T_c of 7.3 K, width-dependent switching characteristics, and a progressive approach of the tunneling limit. In laterally gated Dayem-bridge and nanowire devices, we observe GCS with full suppression of the critical current, where required gate voltages < 5 V promise compatibility with CMOS interfaces. Asymmetries in polarity-dependent power injection via field emission support GCS models that attribute the effect to quasiparticle relaxation through phonon emission. Additional asymmetries in the GCS effect suggest an influence of the substrate condition after dry etching. Field emission features in the gated nanowire device imply superimposed current paths along the gate edge and corners. Finally, we analyze magnetic interference in Dayem-bridge weak links and superconducting quantum interference devices, where quantum interference is governed by Josephson effects and inductance loop asymmetries. Our results contribute to the scaling efforts in hybrid superconducting electronics and quantum-processing units.