FT-CGRA: Compiler-Transparent Fault Tolerance for CGRAs

Research output: Contribution to conferences › Paper › Contributed › peer-review

Contributors

  • Transregio 404: Next Generation Electronics With Active Devices in Three Dimensions

Abstract

Coarse-grained reconfigurable architectures (CGRAs) promise high energy efficiency but remain vulnerable to transient upsets and aging-induced defects. We introduce a compiler-transparent reliability framework that provides online error detection and fast in-field recovery without requiring remapping or software checkpoints. The proposed approach distinguishes transient from permanent faults at runtime and enables rapid handover to healthy resources with low performance overhead. Experimental results demonstrate competitive fault coverage, bounded recovery latency, and negligible impact on steady-state throughput. In addition, a mean time to failure (MTTF) improvement of more than 2.5 is achieved over the baseline without fault tolerance.

Details

Original languageEnglish
Pages117-124
Number of pages8
Publication statusPublished - 2026
Peer-reviewedYes

Conference

Title37th IEEE International Conference on Application-specific Systems, Architectures and Processors
Abbreviated titleASAP 2026
Conference number37
Duration3 - 4 September 2026
Website
LocationImperial College London
CityLondon
CountryUnited Kingdom

External IDs

ORCID /0000-0003-2571-8441/work/228957290
ORCID /0000-0002-8019-7936/work/228957479
Scopus 105052773228

Keywords

Research priority areas of TU Dresden

Sustainable Development Goals

ASJC Scopus subject areas

Keywords

  • B07, Coarse-grained reconfigurable architectures (CGRAs), Fault tolerance, Reliability