FPGA debugging by a device start and stop approach
Research output: Contribution to book/conference proceedings/anthology/report › Conference contribution › Contributed › peer-review
Contributors
Abstract
This paper presents an FPGA debugging methodology based upon a device start and stop (DSAS) approach. Using this approach, the design starts and stops a device under test (DUT) and saves the data to external memory without human interaction. The presented debugging circuit saves data on a trace buffer and once the trace buffer is full, it stops the DUT, saves the data to external memory through Ethernet and then starts the DUT again. Hence the quantity of the debug data is not limited. The contents stored on the external devices can be viewed by open-source waveform viewers or HDL simulators subsequently. The main benefits of the technique are an unlimited debug window, less use of scarce FPGA resources and no loss of debugging data. Neither an external emulation system nor user intervention is required to save the recorded data once the BRAMs are full.
Details
Original language | English |
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Title of host publication | 2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2016 |
Editors | Peter Athanas, Rene Cumplido, Claudia Feregrino, Ron Sass |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (electronic) | 978-1-5090-3707-0 |
Publication status | Published - 2016 |
Peer-reviewed | Yes |
Externally published | Yes |
Conference
Title | 2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2016 |
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Duration | 30 November - 2 December 2016 |
City | Cancun |
Country | Mexico |
External IDs
ORCID | /0000-0003-2571-8441/work/159607578 |
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Keywords
ASJC Scopus subject areas
Keywords
- Debugging, Device Start and Stop, Device under Test, DSAS, DUT, FPGA, Simulation