Energy-Efficient Instruction Delivery in Embedded Systems with Domain Wall Memory

Research output: Contribution to journalResearch articleContributedpeer-review



As performance and energy-efficiency improvements from technology scaling are slowing down, new technologies are being researched in hopes of disrupting results. Domain wall memory (DWM) is an emerging non-volatile technology that promises extreme data density, fast access times and low power consumption. However, DWM access time depends on the memory location distance from access ports, requiring expensive shifting. This causes overheads on performance and energy consumption. In this article, we implement our previously proposed shift-reducing instruction memory placement (SHRIMP) on a RISC-V core in RTL, provide the first thorough evaluation of the control logic required for DWM and SHRIMP and evaluate the effects on system energy and energy-efficiency. SHRIMP reduces the number of shifts by 36% on average compared to a linear placement in CHStone and Coremark benchmark suites when evaluated on the RISC-V processor system. The reduced shift amount leads to an average reduction of 14% in cycle counts compared to the linear placement. When compared to an SRAM-based system, although increasing memory usage by 26%, DWM with SHRIMP allows a 73% reduction in memory energy and 42% relative energy delay product. We estimate overall energy reductions of 14%, 15% and 19% in three example embedded systems.


Original languageEnglish
Pages (from-to)2010-2021
Number of pages12
JournalIEEE Transactions on Computers
Issue number9
Publication statusPublished - Sept 2022

External IDs

ORCID /0000-0002-5007-445X/work/141545513


Research priority areas of TU Dresden

Sustainable Development Goals


  • Benchmark testing, Energy consumption, Magnetic domains, Memory management, Phase change materials, Ports (computers), Transistors

Library keywords