Efficient System-aware Development Strategy for Security-relevant Analog Communication IPs in Smart Systems
Research output: Contribution to book/Conference proceedings/Anthology/Report › Conference contribution › Contributed › peer-review
Contributors
Abstract
Planning, partitioning, and designing highly integrated radio module components for Smart Systems is risky and costly. Reasons include performance-disturbing low-level process effects that are hard to foresee at an early design stage. Thus, a design strategy for embedded RF components has been worked out. It improves and accelerates both design and verification of Smart System architectures especially regarding the crucial analog signal processing parts that suffer most from the process effects and, thus, require much effort. The strategy includes a system-conform provision of a circuit optimization process down a hierarchical design structure. The research presented in this paper resulted in a flexible and efficient design process for embedded RF components.
Details
Original language | English |
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Title of host publication | 2024 Smart Systems Integration Conference and Exhibition (SSI) |
Pages | 1-5 |
Number of pages | 5 |
ISBN (electronic) | 979-8-3503-8877-0 |
Publication status | Published - 16 Apr 2024 |
Peer-reviewed | Yes |
Externally published | Yes |
External IDs
Scopus | 85211595743 |
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Mendeley | 3349b4df-3fef-31dc-bc81-18b16b28f723 |
Keywords
ASJC Scopus subject areas
Keywords
- Analog communication IP, analog design reuse, data converters, design security, system-aware design strategy