As technology scales down, the gate oxid thickness and the channel length is shrunk. This causes greater gate leakage and off-state currents. In consequence of the shorter channel length the supply voltage has to be reduced. To keep the off-state leakage currents within tolerable limits the threshold voltage is not decreased linearly with the supply voltage, but this adversely affects the operating range of the transistor. In order to overcome these degrading effects one has to think of design techniques maintaining the performance of especially analog building blocks. This shall be exemplified with a Delta-Sigma-Modulator, which was implemented and simulated in a 65nm Infineon technology.