In highly-scaled CMOS technologies, analog and digital functionality are often combined into more powerful systems. Implementation of any complex digital circuit requires digital synthesis and therefore a digital standard cell library. Absence of the digital libraries in core design kits provided by the foundries is a significant hurdle for academic institutions to design complex electronic systems. Therefore, design of a custom digital library becomes a necessary step for a successful mixed-signal design. In this paper, the design of such a custom digital library is presented. The library was designed in 28nm CMOS technology and tailored for usage in mixed-signal applications. The composition of available cells and its effect on the performance and area of the synthesized block are discussed. Moreover, different approaches to the transistor dimensioning are compared regarding design effort and performance. To verify the library and the design flow, a serial-to-parallel interface (SPI) demonstrator chip was designed, fabricated and tested. The measurement results correspond to the simulation results and were used to further improve the library and the design process. Finally, the performance of the library is compared to two other digital libraries, one of which is a state-of-the-art commercial library based on high performance 45nm silicon-on-insulator (SOI) CMOS technology. The designed library offers low leakage power and low area consumption while allowing moderate speed which is well suited for the usage in digital control blocks within the mixed-signal systems.