This work presents a class D Power Amplifier (PA) analysis and design in digital CMOS technology. Two topologies of a class D PA were implemented, fabricated and tested under lab conditions. The 1 st topology uses no bandwidth limiting linearization network and demonstrates an ultra-wideband 0 - 11 GHz operation. It features a very compact design, a peak power added efficiency (PAE) of 38 % and a flat output power of P OUT = 10.5 dBm. The 2 nd topology on the other hand, features harmonic filtering on the output side, yielding 2 nd and 3 rd harmonic suppression of 26 dBc and 32 dBc respectively, an output power P OUT = 11 dBm and a peak PAE of 22.5 % within a 1 - 4 GHz bandwidth.