This paper presents the design and implementation of a high speed Low-Voltage-Differential-Signaling (LVDS) transmitter and receiver. Both components are fully compatible to the LVDS standard and are implemented in the standard UMC 180nm CMOS technology. In the framework of the Facets project [3] a wafer-scale configurable spiking neural network is build. Because of the pulse-coupled signal processing, a huge amount of data is generated at many different locations and has to be transmitted to many other locations. Synapses located next to a firing neuron can be connected directly but synapses located far away from a firing neuron need to be connected through a link channel. If many synapses are sharing a single link channel, the data rate is pushed into the gigabit per second range. For this reason the LVDS architecture was chosen for transmitter and receiver.