In this work, the design of a primary Impulse Radio (IR) radar system working in the Ultra-Wideband (UWB) frequency band from 3.1 GHz to 10.6 GHz is presented. It is researched to reduce the latency of positioning systems in a short-range complex environment. State-of-the-Art (SotA) radar works focus mainly on increasing the resolution and the detection range. However, latency is also a relevant aspect. Low latency is critical for many applications, for example, for an Intelligent Traffic System (ITS). This work aims to reduce this latency significantly through latency-oriented system design and optimization in various aspects. The theory of Frequency-Modulated Continuous-Wave (FMCW) and pulse radars is analyzed and compared before the Impulse-Radio Ultra-Wideband (IR-UWB) topology is selected, which has intrinsically high range-resolution and strong immunity against the multi-path effect that is well suited for a short-range complex environment. To reduce the latency, optimization was also performed in aspects of circuit design. The transmitter contains a UWB pulse generator and an amplifier with automatic on-off function. In the receiver part, a 50-dB-gain UWB amplifier using positive feedback for increased bandwidth was carried out. This provides amplified echo signals that can be directly sampled by a 1-bit real-time sampler. The sampler output data stream is fed to a Field-Programmable Gate Array (FPGA), where data processing and warning judgement are performed. The circuit blocks were fabricated and tested individually. Then, a Radio-Frequency (RF) Application Specific Integrated Circuit (ASIC) was designed and taped out. Based on this, the IR-UWB radar system was designed and realized in hardware on a Printed Circuit Board (PCB) mainly including the antennas, the system board and the FPGA module to demonstrate the functionality of the proposed concept. Measurements show that the radar covers a maximum detection range of 15 m. The range resolution is measured down to 3 cm. Furthermore, a target of interest can be warned with a latency as fast as 16 µs by using the 1-bit real-time sampling with a sampling rate of 10 GS/s. The ASIC consumes only 135 mW and occupies 1.9 mm2 using a 45-nm Silicon-on-Insulator (SOI) technology.
|Publication status||Published - 22 Jan 2023|
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