Delay-Based Neural Computation: Pulse Routing Architecture and Benchmark Application in FPGA
Research output: Contribution to book/Conference proceedings/Anthology/Report › Conference contribution › Contributed › peer-review
Contributors
Abstract
Neuromorphic engineering implements large-scale systems that provide a high integration density of power efficient synapse-and-neuron blocks. This represents a promising alternative to the numerical simulations for studying the dynamics of spiking neural networks. A key aspect of these systems is the implementation of communication and routing of pulse events produced by the neural network. In this paper we present a measurement methodology and results of a neural benchmark that tests the configurable delays, multicasting and connectivity implemented by a routing logic for neuromorphic hardware. Pulses are handled according to their timestamp and transmitted with configurable delays and routing to different post-synaptic neurons. The results show the suitability of communication and routing logic for delay-based neural computation and point out effects of time discretization in resolution of pulse timestamps.
Details
Original language | English |
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Title of host publication | 2021 28th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2021 - Proceedings |
Pages | 1-5 |
ISBN (electronic) | 978-1-7281-8281-0 |
Publication status | Published - 2021 |
Peer-reviewed | Yes |
Publication series
Series | IEEE International Conference on Electronics, Circuits and Systems (ICECS) |
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External IDs
Scopus | 85124585131 |
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ORCID | /0000-0002-6286-5064/work/142240656 |
Mendeley | 72f2a1b4-5d15-3cc4-aaf2-ee56429840e2 |
Keywords
ASJC Scopus subject areas
Keywords
- Configurable delays, FPGA, Neural Benchmark, Neuromorphic hardware, Pulse routing