Delay-Based Neural Computation: Pulse Routing Architecture and Benchmark Application in FPGA

Research output: Contribution to book/conference proceedings/anthology/reportConference contributionContributedpeer-review

Abstract

Neuromorphic engineering implements large-scale systems that provide a high integration density of power efficient synapse-and-neuron blocks. This represents a promising alternative to the numerical simulations for studying the dynamics of spiking neural networks. A key aspect of these systems is the implementation of communication and routing of pulse events produced by the neural network. In this paper we present a measurement methodology and results of a neural benchmark that tests the configurable delays, multicasting and connectivity implemented by a routing logic for neuromorphic hardware. Pulses are handled according to their timestamp and transmitted with configurable delays and routing to different post-synaptic neurons. The results show the suitability of communication and routing logic for delay-based neural computation and point out effects of time discretization in resolution of pulse timestamps.

Details

Original languageEnglish
Title of host publication2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Dubai, United Arab Emirates
Pages1-5
ISBN (electronic)978-1-7281-8281-0
Publication statusPublished - 2021
Peer-reviewedYes

Publication series

SeriesIEEE International Conference on Electronics, Circuits and Systems (ICECS)

External IDs

Scopus 85124585131
ORCID /0000-0002-6286-5064/work/142240656

Keywords

Keywords

  • Neuromorphic hardware, Neural Benchmark, Pulse routing, Configurable delays, FPGA